A Bypassable Scan Flip-flop for Low Power Testing with Data Retention Capability

The power consumption of modern highly complex chips during scan test is significantly higher than the consumed functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) proposed for low-power IC flip-flop contains two secondary latches. output “function” latch goes following combinational circuits, while other “shadow” used shift vectors By gating function latch, redundant switching activity in eliminated shift, thereby reducing significantly. suppressed also lower drop across chip, increasing chip manufacturing yield. Furthermore, shadow reused data retention sleep mode performing gating, alleviating area cost latch. BPS-DRFF eases hold time sign-off due elongated clock-to-Q contamination delay that brought by design applied an AES-128 crypto core UMC 55-nm low CMOS technology. Experiment results show 68.5% saved with BPS-DRFF, compared standard flip-flop.